processor pipeline
英 [ˈprəʊsesə(r) ˈpaɪplaɪn]
美 [ˈprɑːsesər ˈpaɪplaɪn]
网络 处理器的流水线; 处理器管线; 流水线
双语例句
- Setting up instructions so that they take full advantage of a processor's pipeline is called instruction scheduling.
对指令进行设置使它们可以充分利用处理器流水线的技术称为指令调度。 - Compared with the full parallel architecture, the memory cost of the designed processor decreases, thus the speed is higher than that of the SDF pipeline architecture.
该处理器内存资源消耗较并行结构有所减少，运算速度较单独的SDF流水线结构有所提高。 - In this paper, we present an universal processor architecture for multi-channel packets encapsulation and forwarding, combined with FPGA embedded memory blocks, pipeline and multi-queue buffer mechanism, which improvs the capability of short packets forwarding at wire-speed or burst flow transfer.
提出了一种通用的多通道报文封装和转发的处理器结构，利用FP-GA内部存储资源，采用流水线和多队列缓存区相结合，显著提高了小报文线速转发和突发流量传输的性能。 - DSP serves as primary processor to control the whole system flow, while FPGA as coprocessor with pipeline parallel processing.
系统由DSP作为主处理器进行全局控制，利用具有流水线并行处理结构的FPGA作为协处理器实时完成DSP分配的处理任务。 - Pipeline Fracture Research of performances of the DLX processor point pipeline for vector processing
管道的断裂问题DLX虚拟处理器流水线向量运算的性能研究 - The paper first introduces architecture adjustment of the DLX processor for pipeline processing and problems by the DLX pipeline, then discusses the performances of the DLX floating point numbers pipeline with examples of its use.
该文先介绍DLX微处理机针对流水线处理的结构调整和流水线面临的问题，然后结合实例，介绍了对DLX浮点数流水线性能的分析研究。 - In this paper, we introduce a simple RISC ISA, Beta ISA, and implement a 3-stage pipeline Beta processor IP core by analyzing pipeline design.
本文对一种简单的32位RISC指令集&Beta指令集进行了介绍，并通过流水线分析与研究，设计实现了基于该指令集的具有三级流水线的处理器IP核。 - This paper discusses the concept of pipeline processor, the problems existed and the design of all the pipeline operation segment during this Hope-Mips designation and development with my participation.
本论文论述了流水线处理器的概念和存在的问题，以及此次参与设计开发的Hope-Mips仿真器中整个流水线操作段的设计。 - This paper presents the theory of neighborhood image processor, and two new modes of the neighborhood function pipeline structure: contract mode and cascade mode.
本文介绍了邻域图像处理机原理，提出了邻域图像处理中新型的收缩型和级联型邻域功能流水线结构。 - The configuration of the real-time processor was introduced, the granularity of the data being processed and its parallel pipeline structure were analyzed.
首先介绍了实时信号处理机的结构，分析了数据处理粒度及其并行流水处理结构。 - This article introduce the principle of Digital Signal Processor, specially refer to basic concept and design technique, include: instruction set, pipeline, memory organization, hardware interface, adder, multiplier, clock strategy, test technique.
阐述了数字信号处理器的原理，重点介绍了设计数字信号处理器芯片的简单概念及设计方法，包括指令集、流水线、存储器组织、硬件接口、加法器、乘法器、时钟方案、测试接口等等。 - At the same time, the graphics processor unit ( GPU) has the feature of high-speed in graphics pipeline and parallelism, and the developed programmable features in recent years have made great potential in general calculate area of the digital image processing.
与此同时，图形处理器（GPU）绘制流水线的高速度和并行性以及近年来发展起来的可编程功能使其在数字图像处理的通用计算领域的应用有着巨大的潜力。 - The processor has 10-stage pipeline structure and the input port of rotating factor in every stage is fixed to improve the rate of processor. Its medium result was stored in dual-port RAM.
处理器采用10级流水线结构，每级将乘法器的旋转因子输入端固定为常数，以进一步提高处理器的速度，而中间结果则以双端口RAM存储。 - Features of different FFT processor constructions especially pipeline& MDC and SDF, is studied combined with algorithm.
本文结合算法研究不同FFT处理器结构的特点，重点研究了流水线结构：MDC和SDF结构。 - Based on the overall consideration of the existing processor, out of order execution and balanced pipeline division are introduced here.
在综合考虑已有处理器机制的基础上，多媒体加速单元整体采用乱序执行和流水线平衡划分的策略。